The reduction of input open-fault in a CMOS Schmitt-Trigger inverter

Authors

DOI:

https://doi.org/10.55674/snrujst.v14i2.245040

Keywords:

CMOS inverter, Self-oscillation, Open-fault, Fail-safe

Abstract

 The failure of the CMOS Schmitt-trigger inverter open-fault and capacitor open-fault in the case of a CMOS Schmitt-trigger inverter oscillator circuit cause a self-oscillation of the device. It leads to the high frequency to be emitted on the output side, because the balance of internal smaller parasitic capacitance approximately 5 – 20 pF. In this article, the reduction of CMOS Schmitt-trigger inverter open-fault and capacitor open-fault in the case of a CMOS Schmitt-trigger inverter oscillator circuit is presented, by adding a capacitor between the Gate pin and Drain pin of Q1 by demonstration illusion of an equivalent circuit. This causes the internal parasitic capacitance to unbalance, then the self-oscillation in the case of input open-fault will not accord. Besides in the case of an oscillator circuit, the feedback resistor is not combined with the internal parasitic capacitance. However, it is combined it is with the added capacitance, the higher frequency self-oscillation does not occur. The circuit was tested with a PSPICE computer simulation program. 

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References

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Published

2022-05-01

How to Cite

Summatta, C., & Rattanangam, W. (2022). The reduction of input open-fault in a CMOS Schmitt-Trigger inverter. Creative Science, 14(2), 245040. https://doi.org/10.55674/snrujst.v14i2.245040