The Comparison of the I-V Characteristic Simulated By Using BSIM3v3 and EKV2.6 Models on Pspice for a MOS Transistor Biased With the Gate-Body Biasing Technique

Abstract

The gate-body biasing technique where the body terminal is floating is a new biasing technique
lately proposed to bias MOS transistor in order to generate log and anti-log functions with a single
MOS transistor. This paper presents the comparison of an I-V characteristic obtained from BSIM3v3
and EKV2.6 models for MOS biased with the new technique. Both models were running on PSpice
simulator. BSIM3v3 and EKV2.6 models are the most commonly used for circuit simulation. The
reference of BSIM3v3 model is the source terminal while for EKV2.6 model is the body terminal.
Due to this difference, it may cause dissimilarity in the I-V characteristic obtained from both models.
Therefore, finding a suitable model to represent this new technique is an essential need for the circuit
designer who wants to apply the gate-body biasing into circuit design. The simulation results show
that a MOS transistor being biased using the new technique from BSIM3v3 and EKV2.6 models can
generate a log function, when the input is voltage (VDS) and an anti-log function when the input is
current (IDS). Moreover, from both models show the similarity in floating voltage between the body
and the source terminals (VBS) which varied with VDS logarithmically; on the other hand, VBS varied
with IDS linearly due to a hole current flowing in the body when current was applied as an input to the
MOS. In conclusion, log and anti-log function generated from a single MOS transistor is possible by
biasing a MOS with the gate-body biasing technique. The simulation results of the I-V characteristics
based on BSIM3v3 and EKV2.6 models agree with each other; therefore, these results ensure that the
possibility of generating log and anti-log functions using just only one device is highly possible.