Low power area efficient self-gated flip flop: Design, implementation and analysis in emerging devices
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Abstract
This study presents a novel CMOS self-gated flip flop for low power and area efficient applications. The low power operations are achieved by deactivating the clock signal when not required in the circuit. The study explores the proposed design in emerging devices like Carbon Nanotube Field Effect Transistor (CNTFET), Graphene Nano-Ribbon FET (GNRFET) and FinFET devices. The simulations are carried out at 16nm technology node in HSPICE with nominal conditions of 0.9 V supply voltage, 25% data activity at temperature of 25 °C and frequency of 400 MHz. Results obtained shows that the proposed design consumed the least power with a reduction of minimum 53.68% and maximum 81.39% at variations in voltages ranging from 0.9 V to 1.2 V. The overall power delay product (PDP) at nominal conditions is reduced by minimum 61.45% and maximum 80.81%. The proposed flip flop is also an area efficient design having least number of transistors and minimum sum of width with average reduced area of 29.55%. The proposed design, when implemented and simulated with emerging devices, showed significant improvements in power consumptions and speed of operations. The simulations confirmed that the FinFET counterpart of the proposed design is most power efficient device whereas GNRFET the least. But the GNRFET is the fastest of all the devices followed by CNTFET at second and FinFET as third fastest whereas CMOS is the slowest among all these devices.
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This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
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