A 1.2V, low-power, and high linear UWB down-conversion CMOS mixer

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Published: May 14, 2021
Keywords:
CMOS Linearity Low voltage mixer Conversion gain Switched buffer

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Mostafa Yargholi
Department of Electrical Engineering, Faculty of Engineering,University of Zanjan, Zanjan, Iran
Farshad Darvishi
Department of Electrical Engineering, Faculty of Engineering,University of Zanjan, Zanjan, Iran

Abstract

A low voltage, high linearity and gain with low power ultra-wideband (UWB) CMOS mixer in the RF receiver is proposed. This mixer is designed for a standard of 802.11 for use in Wi-Fi communications. The linearization technique for the third-order transconductance () cancellation with modified derivative superposition (MDS) is utilized to enhance the linearity performance of the proposed mixer. The MDS technique employs an auxiliary PMOS transistor in parallel with the NMOS transistor in the lower tree (transconductance stage) for reducing the third-order intermodulation distortion (IMD3). Besides, a switched buffer stage and the active loads are employed to improve the conversion gain of the mixer. High gain and high linear mixer is designed by the MDS technique and switched buffer. The proposed mixer is analyzed, and simulated using a 0.18 µm CMOS TSMC process; The LNA achieves 9.1dB conversion gain,  maximum input third-order intercept point (IIP3) of +15dBm, double side-band noise figure (DSB NF) of 15.6 dB. This module consumes 2.06 mW DC power from a 1.2 V power supply in the RF frequency of 10 GHz.

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How to Cite
Yargholi, M., & Darvishi, F. . (2021). A 1.2V, low-power, and high linear UWB down-conversion CMOS mixer. Engineering and Applied Science Research, 48(3), 280–286. Retrieved from https://ph01.tci-thaijo.org/index.php/easr/article/view/240787
Issue
Vol. 48 No. 3 (2021)
Section
ORIGINAL RESEARCH

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This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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