Digital Technique to Generate PWM Signal Using FPGA

Abstract

This paper presents the digital technique to generate a pulse width modulation (PWM) signalusing Field Programmable Gate Arrays (FPGA). In order to reduce the complexity and hardwarerestrictions, the proposed method is performed using program written in Verilog HardwareDescription Language (HDL). The programmed design consists of two counter circuits, comparator,and latch circuit. Setting the value of comparison signal can easily vary the duty cycles of PWM.The frequency of PWM signal is tunable by changing the input clock of counter circuit. In addition,the proposed concept can generate multiple PWM signals with various duty cycles and frequencies atthe same time. Experimental results verifying the performances of the proposed technique are agreedwith the expected values.