การศึกษากระบวนการสร้างและคุณลักษณะทางไฟฟ้าของเอ็นมอสขนาด 0.5 ไมครอน
Keywords:
MOSFET, CMOS, SPICEAbstract
This paper presents a study of the fabrication process and electrical characteristics of 0.5 mm NMOS transistor, n-type Poly silicon gate. There are 3 steps for this study. The first step is fabrication simulation process to predict the electrical properties using Process simulation program, Sentaurus TCAD which is verification program consisting in several conditions of simulation. The goal of the fabrication simulation process is to study the dose concentration of Ion Implantation for p-well and anti-punch through processes that affects the NMOS transistor threshold voltage. The 2nd step is to apply the interesting condition results from the fabrication simulation process for wafer substrate then proceed electrical properties testing of NMOS transistor according to the design conditions including p-well dose concentration 1.0 x 1012 cm-2 threshold voltage adjustment dose concentration 1.8 x 1012 cm-2 and anti-punch through dose concentration 3.0 x 1012 cm-2. As the result, the threshold voltage 0.70 V. with saturated drain current (VDS = VGS = 3.3 V) 403 mA/mm. Finally, these conditions will be applied for extracting the parameter model, spice level 3 which is a useful application for IC designers. The succeeded fabrication of the 0.5 mm NMOS transistor is the recent technology for the smallest NMOS available in Thailand.
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