Voltage-Mode Vector Summation Circuit
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Published:
Feb 18, 2013
Keywords:
vector summation
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Abstract
This paper presents Voltage-Mode Vector Summation Circuit. The circuit can be operated at ± 3
volt supply voltage based on square law characteristic of CMOS operation saturation region. The
input stage is rail to rail operation and has wide input range. There only fourteen sets of MOS
transistors in the circuit. The proposed circuit is simulated by HSPICE. These results agree with the
theory and +3dB bandwidth of 5 MHz
volt supply voltage based on square law characteristic of CMOS operation saturation region. The
input stage is rail to rail operation and has wide input range. There only fourteen sets of MOS
transistors in the circuit. The proposed circuit is simulated by HSPICE. These results agree with the
theory and +3dB bandwidth of 5 MHz
Article Details
How to Cite
Limsuwan, T. (2013). Voltage-Mode Vector Summation Circuit. Engineering and Applied Science Research, 33(4), 349–362. Retrieved from https://ph01.tci-thaijo.org/index.php/easr/article/view/6002
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Section
ORIGINAL RESEARCH
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