Floating-Point Division Operator based on CORDIC Algorithm

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Pongyupinpanich Surapong
Faizal Arya Samman

Abstract

Design and evaluation of a CORDIC (COordinate Rotation DIgital Computer) algorithm for a floatingpoint division operation is presented in this paper. In general, division operation based on CORDIC algorithm has a limitation in term of the range of inputs that can be processed by the CORDIC machine to give proper convergence and precise division operation result. A hardware architecture of CORDIC algorithm capable of processing broader input ranges is implemented and presented in this paper by using a pre-processing and a post-processing stage. The performance as well as the calculation error statistics over exhaustive sets of input tests are evaluated. The results show that the CORDIC algorithm can be well-convergence and gives precise division operation results with broader input ranges. The proposed hardware architecture is modeled in VHDL and synthesized on a CMOS standard-cell technology and a FPGA device, resulting 1 GFlops on the CMOS and 210.812 MFlops on the FPGA device.

Article Details

How to Cite
[1]
P. Surapong and F. A. Samman, “Floating-Point Division Operator based on CORDIC Algorithm”, ECTI-CIT Transactions, vol. 7, no. 1, pp. 79–87, Apr. 2016.
Section
Artificial Intelligence and Machine Learning (AI)