KATOH, Y.; YOSHIUCHI, H.; MURATA, Y.; NAKAJO, H. Scalable Hardware Mechanism for Partitioned Circuits Operation. ECTI Transactions on Computer and Information Technology (ECTI-CIT), [S. l.], v. 12, n. 2, p. 90–97, 2018. DOI: 10.37936/ecti-cit.2018122.142511. Disponível em: https://ph01.tci-thaijo.org/index.php/ecticit/article/view/142511. Acesso em: 5 may. 2024.