An Application of Failure Mode and Effect Analysis (FMEA) Technique in the Final Inspection Process of an Integrated Circuit Industry
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Abstract
The objective of this study is to apply Failure Mode and Effect Analysis (FMEA) to reduce defects in the final inspection process of an integrated circuit industry. Team brain-storming cause-and-effect diagram and FMEA were utilized to investigate the quality of process. Then specialists further analyzed and evaluated level of severity, opportunity of occurrence, and opportunity of defect detection in order to calculate Risk Priority Number (RPN). Two major problems were considered for corrective actions. First problem occurred during machine process setup resulting in possible error in manually loading program by operator. Second problem occurred during loading device into machine process resulting in error in direction checking of tray chamfer. Proposed solutions were to utilize barcode scan on job order to automatically select program from the system, and to redesign instrument to protect wrong tray loading. The factory can benefit from having process guideline, controlling over quality factors, and ensuring the defect will not reoccur. Consequently, rework process was reduced from 20 case/month down to 10 case/month (50%). Cycle time was shortened from 2 hour/lot down to 1.5 hour/lot (25%). Defect was reduced from 2,600 part/million down to 1,300 part/million (50%). Productivity was increased from 1,500 unit/hour up to 1,875 unit/hour.
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